In the fabrication of microelectronic components, a number of the steps involved, for instance, in preparing integrated circuit chips and the packaging for the chips (articles to which the chips are attached and protected), are etching processes. Accordingly, over the years, a number of vastly different types of etching processes to remove material, sometimes in selective areas, have been developed and are utilized to varying degrees. Moreover, the steps of etching different layers which constitute, for instance, the finished integrated circuit chip are among the most critical and crucial steps.
Increasingly, reactive ion etching (RIE), plasma etching and ion milling are being used to define the pattern in a substrate and to form vias. For instance, in complex semiconductor devices such as advanced DRAMS and logic devices with multiple layers of back end of line interconnect wiring, reactive ion etching is used to produce vias through the interlayer dielectric to provide contact between one level of silicon, silicide or metal wiring to the next level of wiring. These vias typically expose Al, AlCu, Cu, Ti, TiN, Ta, TaN, silicon or a silicide such as a silicide of tungsten, titanium or cobalt. The RIE process leaves a residue of a complex mixture that may include re-sputtered oxide material and possibly small amounts of organic material from the resists used to delineate the vias.
It would therefore be desirable to provide a selective cleaning procedure capable of removing the residues caused by the etching and especially a plasma, RIE or ion milling etching. Moreover, it would be desirable to provide a selective cleaning procedure capable of removing the etching residue that exhibits high selectivity for the residue as compared to metal, silicon, silicide and/or interlevel dielectric materials such as deposited oxides that might also be exposed to the cleaning composition.